IEEE section 802.11, which is hereby incorporated by reference in its entirety, defines several different standards for configuring wireless Ethernet networks and devices. For example, 802.11 standards that have been popularized include 802.11(a), 802.11(b) and 802.11(g). Wireless Ethernet network devices may be implemented by a system on chip (SOC) circuit that includes a baseband processor (BBP), a medium access controller (MAC) device, a host interface, and one or more processors. The SOC circuit may include a radio frequency (RF) transceiver or the RF transceiver may be located externally. The host interface may include a peripheral component interface (PCI) although other types of interfaces may be used. The processor(s) may be advanced RISC machine (ARM) processor(s), although other types of processors may be used.
The MAC device controls and selects different operating modes of the BBP and the RF transceiver. During operation, the MAC device instructs the BBP and the RF transceiver to transition to a low power mode to conserve power. The BBP and RF transceivers may include phase-locked loops (PLL). The PLLs are calibrated using a reference signal that is supplied by a crystal oscillator (XOSC). The SOC may also include voltage regulators that provide regulated supply voltages to the system.
The network device is usually associated with a host system (“host”). In an infrastructure mode, the host communicates with a network via the Ethernet network device and an access point (AP). The MAC device typically instructs the BBP and the RF transceiver to transition to the low power mode when the AP and the host do not have data to exchange. However, the voltage regulator in the BBP remains active during the low power mode and still consumes a significant amount of power from digital switching as well as leakage current when advanced deep sub-micron technology is used. Additionally, the XOSC and PLL devices may remain active and also consume power during the low power mode.
In some conventional approaches, the operating voltage and/or the clock frequency are reduced during the low power mode while still allowing the system to operate at full capacity. However, many system components remain active during the low power mode and continue to consume power. In other conventional approaches, the way that functions are implemented is modified to reduce power consumption. For example, the device may lower a frequency of operation so that calculations take longer to complete. However, these system components still continue to consume power even when there are no computations to be performed.